Field effect transistors (FETs) are present in a myriad of electronic devices such as integrated circuits (ICs). An FET includes a source, and a drain electrically connected by a channel. A gate dielectric overlies the channel and a gate electrode, in turn, overlies the dielectric. (A first structure overlies a second structure if the first is farther from the substrate upon which the device is built.) In operation, a voltage is applied to the gate electrode producing, in the absence of a short between the gate electrode and channel through the gate dielectric, a relatively strong electric field. This field causes a change in conduction characteristics of the channel by causing an inversion of dominant carrier type in this region. Accordingly, upon inversion, the current flow between the source and the drain is changed. Indeed, large changes in current flow are inducible by relatively small voltages applied to the gate.
It has been a consistent goal to reduce the size of electronic devices and thus reduce the size of individual FETs in, for example, an integrated circuit. However, as FETs are reduced in size, the dimensions of components including the thickness of the gate dielectric are concomitantly reduced. As the thickness of the gate oxide is reduced, it becomes more difficult to avoid gate dielectric breakdown (i.e. the formation of a current path between the gate electrode and the channel through the gate dielectric).
The occurrence of even a single breakdown of a thick gate dielectric typically produces catastrophic failure of the device due to large changes in the electrical conductivity between the gate and either the source, drain, or substrate resulting in the gating function being severely altered. (A thick gate dielectric in this context is one having an average thickness in the region overlying the channel between the source and drain of more than 50 Å.) Surprisingly, however, for thin gate dielectrics (average thickness of 50 Å or less) the occurrence of a single breakdown (i.e. the presence of a significant increase in the current between gate electrode and channel region at the operating gate voltage), indeed the occurrence of multiple breakdowns, is not generally catastrophic for nominal gate voltages. (See M. A. Alam et al., 2002 IEDM Tech. Digest, pp. 151–154) for a discussion of this phenomenon.) For thin gate dielectrics whether the gate dielectric comprises one, two, three, or more layers at typical gate operating voltages (e.g. less than 2.0 Volts), the presence of a current path through a thin gate dielectric without device failure is denominated soft breakdown. During soft breakdown, a small current flow (generally less than 100 μA) is present between the gate electrode and channel but the device still operates with acceptable electrical characteristics, i.e. the device is still useful for the application in which it is employed.
Nevertheless, as the number of breakdowns increases, in time, the device fails. This time depends on a variety of statistical phenomenon associated with the degradation of the gate dielectric. The ability to determine the average time to failure (and/or the associated statistical distribution) of a device of a particular design is extremely important. Devices that fail in operation in an unacceptably short time will obviously cause undesirable economic consequences. Additionally, even if devices of a specific design on average do not fail prematurely, the unanticipated failure of an individual device might well cause unacceptable results for the user.
In an attempt to determine average device lifetime, accelerated aging tests are generally employed. In such tests, conditions are employed that are substantially more severe than those for which the device is designed. For example, the gate operating voltage is significantly increased, e.g. from 1.2 Volts to 3.3 Volts, and the mean time to failure for a large sample of devices is measured. Alternatively, another accelerated aging test involves increasing the temperature from 125° C. (maximum operating temperature) to more than 150° C. Accelerated testing yields some information concerning reliability, but by itself yields no definitive information concerning the absolute failure time of an individual device. Indeed, over the years, semiconductor manufacturers have developed many extrapolation techniques for thick oxides to correlate the results obtained from accelerated testing to actual operating conditions, but these extrapolation techniques have not proved predictive of thin dielectric reliability. Accordingly an approach to determine the time dependence of operating electrical characteristics in a device with a thin gate dielectric would be quite useful.